Novel dual-Vth independent-gate FinFET circuits

This paper describes gate work function and oxide thickness tuning to realize novel circuits using dual-Vth independent-gate FinFETs. Dual-Vth FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternatives. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than conventional forms, e.g., implementing 12 unique Boolean functions using only four transistors. The gates are designed and calibrated using the University of Florida double-gate model into a technology library. Synthesis results for 14 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average, the enhanced library reduces delay, power, and area by 9%, 21%, and 27%, respectively, over a conventional library designed using FinFETs in 32nm technology.NSF CAREER Award CCF-074685

Dual-Vth Independent-Gate FinFETs for Low Power Logic Circuits

This paper describes the electrode work-function, oxide thickness, gate-source/drain underlap, and silicon thickness optimization required to realize dual-Vth independent-gate FinFETs. Optimum values for these FinFET design parameters are derived using the physics-based University of Florida SPICE model for double-gate devices, and the optimized FinFETs are simulated and validated using Sentaurus TCAD simulations. Dual-Vth FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternative gates with competitive performance and reduced input capacitance in comparison to conventional FinFET gates. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than conventional CMOS gates, e.g., implementing 12 unique Boolean functions using only four transistors. Circuit designs that balance and improve the performance of the novel gates are described. The gates are designed and calibrated using the University of Florida double-gate model into conventional and enhanced technology libraries. Synthesis results for 16 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average at 2GHz, the enhanced library reduces total power and the number of fins by 36% and 37%, respectively, over a conventional library designed using shorted-gate FinFETs in 32 nm technology

Graphene Ambipolar Multiplier Phase Detector

We report the experimental demonstration of a multiplier phase detector implemented with a single top-gated graphene transistor. Ambipolar current conduction in graphene transistors enables simplification of the design of the multiplier phase detector and reduces its complexity in comparison to phase detectors based on conventional unipolar transistors. Fabrication of top-gated graphene transistors is essential to achieve the higher gain necessary to demonstrate phase detection. We report a phase detector gain of −7 mV/rad in this letter. An analysis of key technological parameters of the graphene transistor, including series resistance, top-gate insulator thickness, and output resistance, indicates that the phase detector gain can be improved by as much as two orders of magnitude.NSF CAREER Award CCF-074685

Modeling stochasticity and robustness in gene regulatory networks

Motivation: Understanding gene regulation in biological processes and modeling the robustness of underlying regulatory networks is an important problem that is currently being addressed by computational systems biologists. Lately, there has been a renewed interest in Boolean modeling techniques for gene regulatory networks (GRNs). However, due to their deterministic nature, it is often difficult to identify whether these modeling approaches are robust to the addition of stochastic noise that is widespread in gene regulatory processes. Stochasticity in Boolean models of GRNs has been addressed relatively sparingly in the past, mainly by flipping the expression of genes between different expression levels with a predefined probability. This stochasticity in nodes (SIN) model leads to over representation of noise in GRNs and hence non-correspondence with biological observations. Results: In this article, we introduce the stochasticity in functions (SIF) model for simulating stochasticity in Boolean models of GRNs. By providing biological motivation behind the use of the SIF model and applying it to the T-helper and T-cell activation networks, we show that the SIF model provides more biologically robust results than the existing SIN model of stochasticity in GRNs. Availability: Algorithms are made available under our Boolean modeling toolbox, GenYsis. The software binaries can be downloaded from http://si2.epfl.ch/∼garg/genysis.html. Contact: [email protected]

An Efficient Gate Library for Ambipolar CNTFET Logic

Recently, several emerging technologies have been reported as potential candidates for controllable ambipolar devices. Controllable ambipolarity is a desirable property that enables the on-line configurability of n-type and p-type device polarity. In this paper, we introduce a new design methodology for logic gates based on controllable ambipolar devices, with an emphasis on carbon nanotubes as the candidate technology. Our technique results in ambipolar gates with a higher expressive power than conventional complementary metal-oxidesemiconductor (CMOS) libraries. We propose a library of static ambipolar carbon nanotube field effect transistor (CNTFET) gates based on generalized NOR-NAND-AOI-OAI primitives, which efficiently implements XOR-based functions. Technology mapping of several multi-level logic benchmarks that extensively use the XOR function, including multipliers, adders, and linear circuits, with ambipolar CNTFET logic gates indicates that on average, it is possible to reduce the number of logic levels by 42%, the delay by 26%, and the power consumption by 32%, resulting in a energy-delay-product (EDP) reduction of 59% over the same circuits mapped with unipolar CNTFET logic gates. Based on the projections in [1], where it is stated that defectfree CNTFETs will provide a 5× performance improvement over metal-oxide-semiconductor field effect transistors, the ambipolar library provides a performance improvement of 7×, a 57% reduction in power consumption, and a 20× improvement in EDP over the CMOS library

Power Consumption of Logic Circuits in Ambipolar Carbon Nanotube Technology

Ambipolar devices have been reported in many technologies, including carbon nanotube field effect transistors (CNTFETs). The ambipolarity can be in-field controlled with a second gate, enabling the design of generalized logic gates with a high expressive power, i.e., the ability to implement more functions with fewer physical resources. Reported circuit design techniques using generalized logic gates show an improvement in terms of area and delay with respect to conventional CMOS circuits. In this paper, we characterize and study the power dissipation of generalized logic gates based on ambipolar CNTFETs. Our results show that the logic gates in the generalized CNTFET library dissipate 28% less power on average than a library of conventional CMOS gates. Further, we also perform logic synthesis and technology mapping, demonstrating that synthesized circuits mapped with the library of ambipolar logic gates dissipate 57% less power than CMOS circuits. By combining the benefits coming from the expressive power of generalized logic and from the CNTFET technology, we demonstrate that we can reduce the energy-delay-product by a factor of 20× using the ambipolar CNTFET technology

Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis

This paper exploits the unique in-field controllability of the device polarity of ambipolar carbon nanotube field effect transistors (CNTFETs) to design a technology library with higher expressive power than conventional CMOS libraries. Based on generalized NOR-NAND-AOI-OAI primitives, the proposed library of static ambipolar CNTFET gates efficiently implements XOR functions, provides full-swing outputs, and is extensible to alternate forms with area-performance tradeoffs. Since the design of the gates can be regularized, the ability to functionalize them in-field opens opportunities for novel regular fabrics based on ambipolar CNTFETs. Technology mapping of several multi-level logic benchmarks — including multipliers, adders, and linear circuits — indicates that on average, it is possible to reduce both the number of gates and area by ∼ 38% while also improving performance by 6.9×

Reliability and test of high-performance integrated circuits

textAs high-density, low-cost, high-performance computing devices become more ubiquitous, there is an increased necessity to address the reliable operation of such systems. Both on-line test (concurrent error detection (CED)) and off-line (manufacturing test) techniques contribute to ensuring high levels of product reliability. The first part of this thesis focuses on techniques for CED in integrated circuits. The goal is to develop techniques for the insertion of CED circuitry at higher levels of design abstraction, as well as techniques that make it easier to absorb the associated overhead costs of CED. Approaches for automated design of logic circuits that meet failure rate requirements while minimizing the impact to area, performance, and power are described. The primary emphasis in this thesis is on reducing the soft error failure rate in integrated circuits (which dominates). The latter part of this thesis focuses on off-line test techniques for high-frequency I/O ports in integrated circuits. A low-cost trigger-based solution to eliminate the problem of non-determinism that may arise due to limitations in tester edge placement accuracy during at-speed functional test of high-speed source synchronous I/O ports is described. An analysis of when the problem of non-determinism becomes significant enough to warrant the implementation of the proposed solution is also provided.Electrical and Computer Engineerin